`include "VGA_Controller.v"
`include "div2.v"
module TB_VGA(
/////////////// VGA //////////////////
 VGA_R,
 VGA_G,
 VGA_B,
 VGA_CLK,
 VGA_BLANK,
 VGA_HS,
 VGA_VS,
 VGA_SYNC,
/////////////// CLK //////////////////
 CLOCK_50,
 CLOCK_27,
/////////////// LED //////////////////
 LEDG,
 LEDR,
//////////////////////////////////////
 KEY
); 

/////////////// VGA //////////////////
output			VGA_CLK;   				//	VGA Clock
output			VGA_HS;					//	VGA H_SYNC
output			VGA_VS;					//	VGA V_SYNC
output			VGA_BLANK;				//	VGA BLANK
output			VGA_SYNC;				//	VGA SYNC
output	[9:0]	VGA_R;   				//	VGA Red[9:0]
output	[9:0]	VGA_G;	 				//	VGA Green[9:0]
output	[9:0]	VGA_B;   				//	VGA Blue[9:0]

/////////////// CLK //////////////////
input			CLOCK_27;				   //	27 MHz
input			CLOCK_50;				   //	50 MHz

/////////////// LED //////////////////
output	[8:0]	LEDG;					   //	LED Green[8:0]
output	[17:0]	LEDR;					//	LED Red[17:0]

/////////////// KEY //////////////////
input [3:0] KEY;

//init

initial
 begin
    $dumpfile("test.vcd");
    $dumpvars(0,TB_VGA);
 end

reg reset = 1;
wire z;
reg clk = 0;

always begin
  #1 clk = ~clk;
end

//assign reset = KEY[3];

initial begin
  #1 reset = 0;
  #5 reset = 1;
end

div2 clk_div (.clk_50(clk),.clr(reset),.z(z));

VGA_Controller vgacontrol(.RESET(reset),
			   .CLK(clk),
			   .VGA_CLK(VGA_CLK),
			   .VGA_HS(VGA_HS),
			   .VGA_VS(VGA_VS),
			   .VGA_BLANK(VGA_BLANK),
			   .VGA_SYNC(VGA_SYNC),
			   .VGA_R(VGA_R),
			   .VGA_G(VGA_G),
			   .VGA_B(VGA_B)
			  );

endmodule